1. Field of the Invention
This invention relates to procedures for accurately defining very small geometries, on the order of down to about 50 angstroms, in the fabrication of semiconductor devices.
2. Brief Description of the Prior Art
As the geometries of semiconductor devices become increasingly smaller, photolithographic techniques are becoming increasingly less capable of coping with the requirement to accurately define the geometry of gate lengths and contact openings in the fabrication of such devices. This problem is particularly acute when viewed from an economic perspective. Accordingly, there is a continuing effort in the art of semiconductor fabrication to resolve this problem and the present invention is a continuation of this effort.
It is known that the geometries of sidewall depositions can be very closely controlled on an economic basis in view of the fact that the sidewall thicknesses can be very well controlled down to thicknesses in the tens of angstroms. The formation and use of sidewall oxides in particular have been well known in the art for many years. It is also known in the prior art to use sidewall spacers on the gates of MOSFETs to separate the source/drain implant from the channel region and to separate the source/drain silicide from the gate silicide. It is further known to use sidewall layers to form narrow gate structures.